Muhammad Salman Afzal
NUST
· 2021
Email
m.salmanafzal@hotmail.com
Phone
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GitHub
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Academic
Program
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CGPA
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Year
2021
Education
Punjab College of Science, Faisalabad
'17
FSc
Divisional Public School & College, Faisalabad
'15
Matric
June'19
Summer Intern | RISC Lab, SEECS, NUST
Aug'19
--Learn about Verilog as Hardware Descriptive Language
--Implement general Hardware problems in Verilog
--Learn about Hardware designing of RISC-V ISA
--Implementing a general purpose parameterized RISC-V core in Verilog and
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i i
Freelancer | Fiverr
Sep'19
Sep'20
--Work related to Computer Architecture of MIPS and RISC-V ISA
--Digital Logic and System Designing in Verilog and SystemVerilog
Address
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DOB
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AI enrichment
Deterministic and passionate individual, proficient in hardware circuits design using Verilog or System Verilog and currently working on Verification of RISCV based designs. I’ve also worked on embedded microcontrollers like ARM. My goal is to bring the semi-conductor industry to our country and make it independent. I hope to work in a friendly yet competitive environment that enables you to do more. National Institute of Sciences & Technology, Islamabad '21 BS Electrical
Status: ai_done
Provenance
Source file: —Created: 1777448794