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Abdullah Mir

NUST · 2022

mirabdullah0001@gmail.com

Phone

03231223357

https://linkedin.com/in/-abdullahmir

GitHub

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Academic

Program

Electrical engineering

CGPA

3.0

Year

2022

Education

seecs

Address

HOUSE NO 5D Y BLOCK SCHEME NO.2 CHAH MIRAN LAHORE , Lahore , Pakistan

DOB

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Career

Current role

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Target role

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Skills

C/C++, STM32, ESP32, Arduino, FPGA, Post-quantum cryptography, ASCON, CPU design, SystemVerilog, Embedded Systems, Digital Design, Verilog, Vivado, Quartus, ASIC flow, Floorplanning, STA, PPA trade-offs, Linux kernel modules, Character drivers, File ops, Ioctl, UART, SPI, I2C, PCB design, Proteus, Raspberry Pi, Sensors, MOSFETs, BJTs, Voltage regulators

Verbatim text

The exact text the LLM saw on the page (or the booklet text from the old import). This is what powers semantic search.

Abdullah Mir
Cell: 03231223357 | Email: mirabdullah0001@gmail.com
LinkedIn: https://linkedin.com/in/-abdullahmir
Address: HOUSE NO 5D Y BLOCK SCHEME NO.2 CHAH MIRAN LAHORE , Lahore , Pakistan
PROFESSIONAL PROFILE
Embedded Systems and Digital Design enthusiast with hands-on experience in C/C++, microcontrollers (STM32,
ESP32, Arduino), and FPGA-based hardware accelerators. Worked on post-quantum cryptography (ASCON)
accelerators, CPU design in SystemVerilog, and real-time embedded projects using sensors and communication protocols.
Strong in self-learning, documentation, and explaining complex concepts to others.
EDUCATION
Electrical engineering
seecs , Islamabad , 3.0 (2022)
INTERNSHIP EXPERIENCE
SOC lab/Nstp/NUSt
01-Apr-2025 - 14-Jan-2026
• Worked on hardware accelerators for PQC (ASCON-128), focusing on side-channel resistance and secure hardware for embedded
systems. • Veriﬁed ASCON in C using NIST vectors and integrated with FPGA ﬂow (Vivado/Quartus). • Designed simple CPU in
SystemVerilog (ALU, regﬁle, decoder, control), veriﬁed via RTL simulation & synthesis. • Exposure to ASIC ﬂow – ﬂoorplanning, STA,
PPA trade-offs. • Performed literature review and contributed to research publication.
SDAC, Embedded Systems Research Lab – NUST
01-Jun-2024 - 01-Aug-2024
• Built FPGA-based solutions on DE1-SoC integrating ARM Cortex-A9 with custom logic for embedded applications. • Developed
Linux kernel modules/character drivers for custom peripherals using ﬁle ops & ioctl. • Interfaced sensors & peripherals using C/C++
with interrupts, polling, and MMIO. • Worked with UART, SPI, I2C; debugged using logs & test utilities.
QKZEE Technologies
01-Apr-2023 - 01-Sep-2023
• Assembled and tested electronic circuits using soldering, PCB design workﬂows, and Proteus simulations, supporting academic and
IoT-based hardware projects. • Developed microcontroller-based prototypes on Arduino, ESP32, and Raspberry Pi, integrating
ultrasonic, IR, temperature, humidity, gas, and motion sensors. • Implemented power regulation and switching circuits using
MOSFETs, BJTs, voltage regulators, capacitors, and batteries ensuring safe and stable device operation. • Debugged hardware
issues including noisy signals, incorrect pin mapping, unstable power, and coding errors.
FINAL YEAR PROJECT
sharp: secure hardware accelerator for post quantum cryptography algorithms
This Final Year Project focuses on the design and implementation of SHARP (Secure Hardware Accelerator for Post-Quantum
Cryptography), a dedicated cryptographic accelerator targeting ASCON-128a, a NIST-standardized lightweight post-quantum
cryptographic algorithm. The objective of SHARP is to enable secure, eﬃcient, and side-channel-resistant communication for
resource-constrained IoT and embedded systems in the post-quantum era. The project explores and evaluates three architectural
approaches for ASCON-128a implementation: single-cycle, multi-cycle, and pipelined architectures, with a detailed analysis of power, performance, and area (PPA) trade-oﬀs. Based on these evaluations, a potential hybrid architecture is being investigated to further optimize eﬃciency while maintaining security guarantees. A strong emphasis is placed on hardware-level side-channel resistance, ensuring robustness against physical attacks such as power analysis. The ﬁnal deliverable is a synthesizable chip-level design suitable for integration into IoT platforms, enabling secure communication in the quantum computing era. Currently, the SHARP

AI enrichment

Abdullah Mir is an Electrical Engineering graduate with specialized experience in embedded systems, FPGA design, and hardware accelerators for post-quantum cryptography. His background includes internships at NUST and QKZEE Technologies, where he developed custom CPU designs, Linux kernel modules, and IoT prototypes using C/C++ and SystemVerilog.

Skills (AI)

["C/C++", "SystemVerilog", "FPGA Design", "Embedded Systems", "Microcontrollers (STM32, ESP32, Arduino)", "Linux Kernel Modules", "Hardware Accelerators", "Post-Quantum Cryptography", "PCB Design", "Communication Protocols (UART, SPI, I2C)"]

Status: ai_done

Provenance

Source file: SEECS - Electrical Engineering-2026.pdf
From job #259 page 108
Created: 1778168427