Qasim naeem
NUST
· 2023
Email
qasimnaeem364@gmail.com
Phone
03137821460
LinkedIn
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GitHub
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Academic
Program
BEE
CGPA
3.28
Year
2023
Education
SEECS
Address
Sialkot, Pakistan
DOB
—
Career
Current role
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Target role
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Skills
Vivado, C++, python, assembly, Modelsim, xilinx ise, fpga, Matlab, wireshark, sublime, Hdl/vhdl, Ros, Verilog programming, Communication skills, Team management skills, Flexibility and adaptability, Effective leadership and manag
Interests / quote
My objective is to persue my career in the field of ASIC Design and Verification (UVM). I aim to join a company in which I can grow professionally and polish my skills.
Verbatim text
The exact text the LLM saw on the page (or the booklet text from the old import).
This is what powers semantic search.
Qasim naeem . Details Technical Skills Soft Skills Reference Cell: 03137821460 Email: qasimnaeem364@gmail.com Address: VILLAGE AND POST OFFICE SATRAH TEH DASKA DIST SIALKOT Sialkot , Pakistan Vivado C++, python, assembly Modelsim, xilinx ise, fpga Matlab, wireshark, sublime Hdl/vhdl Ros,python,vhdl,c++,assembly Verilog programming Communication skills Team management skills Flexibility and adaptability Effective leadership and manag To be furnished upon request. Professional Profile My objective is to persue my career in the field of ASIC Design and Verification (UVM). I aim to join a company in which I can grow professionally and polish my skills. Education BE Electrical Engineering School of Electrical Engineering and Computer Science (SEECS) , 3.28 SSC-Matric Quaid Public High School , 1034/1100 (2017) FSc Pre-Engg Punjab College of Science , 924/1100 (2019) Internship Experience Dreambig Semiconductors ( 25-Jul-2022 - 11-Sep-2022 ) I got training of System Verilog based Universal Verification Methodology (UVM) in my six week internship period and build a verification environment for Axi-stream-fifo IP of Vivado. IC Design Lab SEECS ( 31-Jul-2021 - 11-Sep-2021 ) I did a 6 week internship under supervision of Dr Rehan Ahmad and learned Verilog and VHDL during this period. Projects RISC V Integer ISA Implementation on FPGA We implemented Single Cycled RISC-V architecture Integer ISA on DE-10 lite FPGA board in this project. Bresenham Circle Drawing Algorithm on FPGA ( Quartus ) I implemented a circle drawing algorithm on DE-1 FPGA board and displayed using VGA. UVM Environment for AXI-Stream-FIFO IP of Vivado (UVM/SystemVerilog) In my six week internship at Dreambig Semiconductors , I learned UVM and implented my knowledge to build a Verification Environment for AXI-Stream-FIFO.
AI enrichment
Qasim Naeem is an Electrical Engineering graduate with a focus on ASIC Design and Verification, specifically in UVM and SystemVerilog. He has completed internships involving FPGA implementation and verification environment development for AXI-Stream-FIFO IP.
Skills (AI)
["SystemVerilog", "UVM", "Verilog", "VHDL", "FPGA", "C++", "Python", "Assembly", "Vivado", "Modelsim", "Xilinx ISE", "MATLAB", "Wireshark", "ROS", "RISC-V", "AXI-Stream-FIFO"]
Status: ai_done