Abdullah Siddiqui
NUST
· 2025
Email
asiddiqui.bee21seecs@seecs.edu.pk
Phone
923366445844
LinkedIn
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GitHub
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Academic
Program
BEE
CGPA
3.49
Year
2025
Education
SEECS
Address
40 CM, Y BLOCK, PEOPLES COLONY Gujranwala , Pakistan
DOB
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Career
Current role
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Target role
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Skills
Operating systems, Embedded c, Freertos & mbed rtos, C++, python, assembly, Modelsim, xilinx ise, fpga, Tensorflow, keras, pytorch, Matlab, Verilog programming, Strategic communications, Analytical thinking, Strong work ethics, Initiative and enterprise, Teamwork, flexibility, Microsoft word, excel, project, Team management skills, Freelance writer
Interests / quote
Skilled at computer architecture, digital design and embedded software, with experience in deep learning and signal processing. Always willing to learn new skills and explore new ideas, and I thrive in team-based, highly social environments.
Verbatim text
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This is what powers semantic search.
Abdullah Siddiqui Cell: 923366445844 Email: asiddiqui.bee21seecs@seecs.edu.pk Address: 40 CM, Y BLOCK, PEOPLES COLONY Gujranwala , Pakistan Operating systems Embedded c Freertos & mbed rtos C++, python, assembly Modelsim, xilinx ise, fpga Tensorflow, keras, pytorch Matlab Verilog programming Strategic communications Analytical thinking Strong work ethics Initiative and enterprise Teamwork, flexibility Microsoft word, excel, project Team management skills Freelance writer To be furnished upon request. Professional Profile Skilled at computer architecture, digital design and embedded software, with experience in deep learning and signal processing. Always willing to learn new skills and explore new ideas, and I thrive in team-based, highly social environments. Education BE Electrical Engineering School of Electrical Engineering and Computer Science , 3.49 , (2019) , (2021) Cambridge A Level Beaconhouse Palm Tree Campus , 3A*, 1B (2021) Cambrigde O Level. Cadet College Hasanabdal , 8A*, 1A (2019) Internship Experience NUST Chip Design Centre - SOC Lab ( 20-Jun-2024 - 06-Sep-2024 ) Interned under the supervision of Dr. Muhammad Imran. Researched state-of-the-art cores, open-source RISC-V softwares. Literature review of state-of-the-art prefetchering and cache-replacement algorithms and memory system design. Projects Cache Prefetching for RISC-V (Final Year Project) Comparative analysis of combined efficiency of cache prefetching and repalcement algorithms via ChampSim. Design, implementation and integration of fully functional memory system and pipelined, out-of-order RISC-V core using Verilog HDL. ReachAble - Gesture Controlled Robot. FICS Project. Use of ESP32 and FreeRTOS to create helper robot controlled remotely via a glove equipped with flex sensor. Target market includes elderly and differently abled individuals. Parameterized Serial RISC-V Design of a parameterized, serial RISC-V processor for application in low-power, limited area systems using Verilog HDL Self Mixing Interferometry Using Deep Learning Research Project. Create a synthetic dataset for SMI power signal via MATLAB. Provide a comparative approach of predicting displacement via laser feedback systems through various deep learning models, including vanilla RNNs, LSTMs, Transformers etc.
AI enrichment
Abdullah Siddiqui is a recent Electrical Engineering graduate with a strong focus on embedded systems, digital design, and RISC-V architecture. He has practical experience in FPGA development, FreeRTOS, and deep learning applications through academic projects and a research internship.
Skills (AI)
["C", "C++", "Python", "Verilog", "RISC-V", "FPGA", "FreeRTOS", "Embedded Systems", "Deep Learning", "TensorFlow", "PyTorch", "MATLAB", "Assembly"]
Status: ai_done