Muqaddas Masood

NUST · 2026

muqaddasmasood802@gmail.com

Phone

923435182759

https://www.linkedin.com/in/muqaddas-masood-422312291?utm_source=share&utm_campaign=share_via&utm_content=profile&utm_medium=android_app

GitHub

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Academic

Program

BE Electrical Engineering

CGPA

3.53

Year

2026

Education

School of ELectrical Engineering and Computer science (NUST)

Address

Pakistan

DOB

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Career

Current role

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Target role

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Skills

FPGA Development, IC design, Research, Embedded Systems, Verilog HDL, Hardware and software co-design, Microcontroller-based system development, Vivado, Synthesis, Implementation, Timing analysis, HLS Development, C/C++ to RTL, Pipelining, Optimization, ARM FPGA integration, AXI, IP-based systems, Botpress, API Integration, YOLOv8-Nano, High-Level Synthesis (HLS), Parallel processing, Memory management

Interests / quote

I am a motivated electrical engineering student with a strong interest in FPGA development, IC design, research, and embedded systems. I aim to apply my skills in Verilog HDL, hardware and software co-design,and microcontroller-based system development to contribute to innovative engineering solutions while expanding my research and hands-on design experience.

Verbatim text

The exact text the LLM saw on the page (or the booklet text from the old import). This is what powers semantic search.

Muqaddas Masood
Cell: 923435182759 |  Email: muqaddasmasood802@gmail.com
LinkedIn: https://www.linkedin.com/in/muqaddas-masood-422312291?
utm_source=share&utm_campaign=share_via&utm_content=profile&utm_medium=android_app
Address: , Pakistan
PROFESSIONAL PROFILE
I am a motivated electrical engineering student with a strong interest in FPGA development, IC design, research, and embedded
systems. I aim to apply my skills in Verilog HDL, hardware and software co-design,and microcontroller-based system development to
contribute to innovative engineering solutions while expanding my research and hands-on design experience.
EDUCATION
BE Electrical Engineering
School of ELectrical Engineering and Computer science (NUST) , Islamabad , 3.53 (2026)
INTERNSHIP EXPERIENCE
NECOP
14-Jul-2025 - 14-Sep-2025
DMA Loopback Project Implemented and tested a DMA loopback design on FPGA, conﬁguring AXI interfaces to validate high-speed
data transfers. Gained hands-on experience in FPGA prototyping, simulation, and hardware debugging, while strengthening
understanding of system-level design and verification.
Octaloop
01-Jul-2024 - 19-Aug-2024
Developed an AI-powered chatbot using Botpress, integrating API keys to enable smooth and dynamic user interactions.
Pakistan Railway
26-Aug-2024 - 07-Sep-2024
Railway Workshop: Participated in a two-week workshop focused on the electrical setup and power distribution in trains. Gained
hands-on experience through industrial visits, learning about the intricate systems that power trains and their operations in real-world
environments.
FINAL YEAR PROJECT
High-Speed AI Accelerator on FPGA for Real-Time Applications
This project focuses on implementing the YOLOv8-Nano object detection algorithm on an FPGA using High-Level Synthesis (HLS) to
achieve real-time performance for edge applications. YOLOv8-Nano is a lightweight and eﬃcient deep learning model designed for
fast object detection with reduced computational complexity. The project involves converting key neural network layers such as
convolution, batch normalization, activation, and feature map processing into hardware-accelerated modules using HLS, while the
control and system integration are handled through an embedded processor. The design emphasizes parallel processing, pipelining,
and eﬃcient memory management to optimize latency, throughput, and FPGA resource utilization. The ﬁnal system will be capable of
performing real-time object detection for applications such as surveillance, autonomous systems, and smart embedded devices,
while also serving as a research platform for future ASIC and AI accelerator development.
TECHNICAL EXPERTISE
FPGA Design
Vivado, Verilog HDL, synthesis, implementation, timing analysis HLS Development C/C++ to RTL using Vivado HLS, pipelining,
optimization,ARM FPGA integration, AXI, IP-based systems.

AI enrichment

Muqaddas Masood is a final-year Electrical Engineering student at NUST with a focus on FPGA development, IC design, and embedded systems. She has practical experience in Verilog HDL, HLS, and AXI interface configuration through internships and a final year project on AI acceleration.

Skills (AI)

["FPGA Design", "Verilog HDL", "High-Level Synthesis (HLS)", "Vivado", "C/C++", "AXI Interfaces", "Embedded Systems", "Hardware Debugging", "System Verification"]

Status: ai_done

Provenance

Source file: SEECS - Electrical Engineering-2026.pdf
From job #259 page 5
Created: 1778168427