← Back to cohort

Abdullah Awais

NUST · 2026

abdu79311@gmail.com

Phone

923234358547

https://www.linkedin.com/in/abdullah--awais/

GitHub

—

Academic

Program

Electrical Engineering

CGPA

3.55

Year

2026

Education

SEECS

Address

70/A-1 MODEL TOWN, LAHORE , Lahore , Pakistan

DOB

—

Career

Current role

—

Target role

—

Skills

MATLAB, C/C++, Object-Oriented Programming, AVR Development, RTL Design, Digital Logic Design, Fritzing, Python, Verilog, RISC-V Assembly, Computer Architecture, ESP32, ESP8226, Arduino, IoT, UVM

Verbatim text

The exact text the LLM saw on the page (or the booklet text from the old import). This is what powers semantic search.

Abdullah Awais
Cell: 923234358547 |  Email: abdu79311@gmail.com
LinkedIn: https://www.linkedin.com/in/abdullah--awais/
Address: 70/A-1 MODEL TOWN, LAHORE , Lahore , Pakistan
PROFESSIONAL PROFILE
Motivated 8th-semester Electrical Engineering student with strong programming skills in MATLAB, C/C++, object-oriented
programming, and AVR development. Experienced in RTL design and digital logic development, with a solid foundation in
hardware-level system implementation. Proﬁcient in simulation development, digital system modeling, and schematic design
using tools such as Fritzing. Passionate about developing eﬃcient hardware-centric solutions and eager to further deepen expertise
in embedded systems, IoT, RTL-based system design, and advanced digital engineering technologies.
EDUCATION
Electrical Engineering
School of Electrical Engineering and Computer Science , Islamabad , 3.55 (2026)
INTERNSHIP EXPERIENCE
Nust Chip Design Centre
10-Jun-2025 - 29-Aug-2025
Training Labs and Assignments in C/C++, Digital Logic Design (DLD), RISC-V Assembly, and Computer Architecture and worked on
the project 'RTL to GDS-II design of AES Rijndael block cipher'.
FINAL YEAR PROJECT
ASIC design of AES Rijndael
The project involves designing an Application-Speciﬁc Integrated Circuit (ASIC) for the AES Rijndael cipher, a widely used encryption
standard. The aim is to deliver a high performance GDS-II ﬁle of the AES block cipher and verify it using the Universal Veriﬁcation
Methodology (UVM)
TECHNICAL EXPERTISE
Programming
Strong programming proﬁciency in C/C++, Python, and MATLAB, with experience in algorithm implementation, numerical analysis,
and engineering simulations.
Digital & RTL Design
Experienced in Verilog-based RTL design, digital circuit implementation, and functional verification through simulation and debugging.
Debugging & Problem Solving
Strong debugging skills with the ability to analyze hardware and software issues, trace root causes, and implement effective fixes.
Circuit Design & Analysis
Proficient in circuit designing and analysis, including component selection, schematic development, and performance evaluation.
Embedded & IoT Systems
Hands-on experience in IoT system development using ESP32, ESP8226, and Arduino, including sensor interfacing and
communication protocols.

AI enrichment

Abdullah Awais is an 8th-semester Electrical Engineering student with a 3.55 CGPA, specializing in digital logic, RTL design, and embedded systems. He has practical experience through an internship at the NUST Chip Design Centre and a final year project focused on ASIC design for the AES Rijndael cipher.

Skills (AI)

["C/C++", "Python", "MATLAB", "Verilog", "RTL Design", "Digital Logic Design", "RISC-V Assembly", "Computer Architecture", "ASIC Design", "UVM", "Embedded Systems", "IoT", "ESP32", "Arduino", "Schematic Design", "Fritzing"]

Status: ai_done

Provenance

Source file: SEECS - Electrical Engineering-2026.pdf
From job #259 page 8
Created: 1778168427