Irfa Farooq

Academic

Career

Verbatim text

Irfa Farooq
Cell: 03105644665 |  Email: i.am.irfa.misashi@gmail.com
LinkedIn: https://www.linkedin.com/in/irfa-farooq-361507224/
Address: HOUSE NUMBER 461-A PAK BLOCK IQBAL TOWN LAHORE , Lahore , Pakistan
PROFESSIONAL PROFILE
I am an Electrical Engineering undergraduate with a strong inclination toward digital design and low-level system development,
particularly in the area of processor and accelerator architectures. I am motivated by understanding how architectural decisions
translate into real performance and correctness at the hardware level, and I prefer working close to the RTL where design choices
have measurable impact. My academic journey and hands-on project work have shaped a design-first mindset, complemented by a
growing appreciation for disciplined verification as an essential part of building reliable digital systems.
I have previously been associated with the NUST Chip Design Centre (NCDC), where early exposure to chip-level thinking, processor
fundamentals, and structured engineering workflows helped solidify my interest in processor design and verification. Since then, I
have continued to refine my technical direction through advanced coursework and project-driven learning, with an emphasis on
writing, analyzing, and improving digital designs rather than treating them as black boxes.
At present, my objectives are centered on developing into a capable digital design engineer who can contribute meaningfully to
processor and accelerator development teams. Alongside design, I am intentionally strengthening my verification skills to ensure
correctness and robustness in complex systems. In parallel, I am building foundational knowledge in machine learning to better
understand modern compute workloads from a hardware execution perspective, with the long-term goal of working on hardware that
is informed by, and optimized for, emerging ML-driven applications.
EDUCATION
Bachelors in electrical engineering (BEE)
School of Electrical Engineering and Computer Sciences (SEECS) , Islamabad , 3.61/4.0 (2026)
INTERNSHIP EXPERIENCE
NUST Chip Design Centre (NCDC)
10-Jun-2025 - 29-Aug-2026
I begin working with NUST Chip Design Centre (NCDC) as a trainee in February, where I underwent structured training in core areas
of digital design, computer architecture, and embedded systems. During this phase, I focused on strengthening my fundamentals in
C/C++, Digital Logic Design, RISC-V assembly, and processor-level concepts, with particular emphasis on understanding instruction
execution, datapath behavior, and hardware–software interaction. This period provided the foundational knowledge required to
transition into hands-on RTL and processor-related work. Following the training phase, I continued at NCDC as a summer intern,
where the focus shifted toward practical application of the acquired concepts. During the internship, I worked on processor-oriented
tasks involving RTL design exposure, instruction decoding concepts, and microarchitectural understanding of RISC-based systems. I
gained hands-on experience with hardware description languages, simulation workflows, and system-level thinking required for
processor integration and verification. The internship helped bridge theoretical knowledge with real-world chip design practices and
played a significant role in shaping my interest in digital design, processor microarchitecture, and design verification.
FINAL YEAR PROJECT
Performance Enhanced Implementation of a RISC-V Vector Processor
The Final Year Project focuses on the performance-oriented redesign of a RISC-V vector processor to address throughput limitations
observed in a baseline single-lane, 32-bit implementation. The work concentrates on architectural and RTL-level enhancements
aimed at improving execution efficiency for compute-intensive workloads. A key aspect of the project involves redesigning the vector
core to incorporate memory banking mechanisms that reduce memory access contention and enable higher data throughput. In
parallel, instruction-level parallelism is explored by identifying and packing independent vector instructions for concurrent execution,
thereby improving utilization of vector resources and reducing overall cycle counts. The project also involves contributing to datapath

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