Muhammad Umair Ajmal

Academic

Career

Verbatim text

Muhammad Umair Ajmal
Cell: 923080246699 |  Email: mumairajmal786@gmail.com
LinkedIn: https://www.linkedin.com/in/muhammad-umair-ajmal-ab566225b
Address: CHAK NO. 254-J.B TEHSIL & DIST. JHANG , Jhang , Pakistan
PROFESSIONAL PROFILE
Final Year Electrical Engineering student at NUST specializing in FPGA-based digital systems, SoC architectures, and Edge-AI
acceleration. Hands-on experience through internships at NUST Chip Design Centre (NCDC) and SoC Lab, working on RTL
design, processor architecture, and AI-oriented hardware systems. Strong foundation in Verilog/SystemVerilog, C/C++, RISC-
V, and Machine Learning, Deep Learning, and Computer Vision, with an active Final Year Project focused on FPGA-powered
real-time medical diagnosis and automated report generation using CNNs and LLMs.
EDUCATION
Bachelor of Electrical Engineering
School of Electrical Engineering and Computer Science, NUST , Islamabad , 3.14/4.00 (2022 – 2026)
INTERNSHIP EXPERIENCE
Nust Chip Design Centre (NCDC), NUST
10-Jun-2025 - 29-Aug-2025
Completed structured training in C/C++, Digital Logic Design, RISC-V Assembly, and Computer Architecture. Contributed to SoC-
level AI project, implementing Vision Transformers for clinical data classification. Developed and tested modules for attention
mechanisms, cross-attention layers, and dataflow pipelines on simulation. Gained hands-on experience in hardware-software co-
design, understanding latency, throughput, and memory optimization for AI workloads. Collaborated in a team environment,
practicing version control, code reviews, and testbench-driven verification.
System On Chip (SOC) Lab, NUST
23-Jun-2024 - 10-Aug-2024
Designed and implemented a real-time FPGA-based digital clock using Verilog HDL. Developed a custom 8-bit processor
architecture, including datapath, ALU, and control unit, validated via simulation. Implemented finite state machines (FSMs) and
performed timing analysis for clocked operations. Worked on RTL simulation, synthesis, and verification to ensure correct
functionality. Strengthened skills in FPGA prototyping, resource utilization optimization, and debugging.
FINAL YEAR PROJECT
Edge-AI Accelerator: FPGA-Powered Real-Time Diagnosis and Report Generation
Designing an FPGA-based Edge-AI accelerator on Xilinx Virtex-7 for real-time medical diagnosis. Implementing Convolutional Neural
Networks (CNNs) for image classification on FPGA. Using tools like Vivado, Vivado HLS for implementation. Exploring parallelism,
pipelining, and memory optimization for high-throughput, low-latency inference. Integrating Large Language Models (LLMs) to
generate automated clinical reports from diagnosis outputs. Experimenting with FPGA resource allocation, BRAM utilization, and
DSP optimization to accelerate AI workloads.
TECHNICAL EXPERTISE
Hardware & FPGA Design
Verilog, SystemVerilog, RTL Design, FSMs, ALUs, Multipliers, Custom Processor Design, FPGA Prototyping, Timing-Aware Design,
Resource Optimization, SPI, and Digital Interfaces
Computer Architecture & SoC
RISC-V Assembly and Simulation. Datapath and Control Unit Design. Hardware–Software Co-Design and Optimization. RISCV

AI enrichment