Ahmad Abdullah

Academic

Career

Verbatim text

Ahmad Abdullah
Cell: 03330900060 |  Email: hamzaizgreat42@gmail.com
LinkedIn: https://www.linkedin.com/in/ahmad-abdullah-5205a71a5/
Address: HOUSE#299, STREET#2, SECTOR C, SAFARI HOMES, 8,PHASE BAHRIA TOWN, RAWALPINDI , Rawalpindi , Pakistan
PROFESSIONAL PROFILE
To build a strong and successful career in the field of engineering and technology.
To apply my knowledge, skills, and problem-solving abilities in a professional working environment.
To gain practical experience and continuously improve my technical and analytical skills.
To work in a challenging environment focused on digital systems, embedded systems, and hardware design.
To contribute to projects involving processor design, digital ICs, and modern electronic systems while growing as an
engineer.
EDUCATION
Electrical Engineering
National University fo Sciences and Technology , Islamabad , 3.06 (2026)
INTERNSHIP EXPERIENCE
NUST Chip Design Center
09-Jun-2025 - 28-Aug-2025
We covered labs and exams on the following four modules: 1. C Programming 2. Digital Logic Design 3. RISC-V Assembly Language
4. Computer Architecture
FINAL YEAR PROJECT
ASIC Design of Advanced Encryption Standard (AES)
This project presents an ASIC design of the Advanced Encryption Standard (AES) aimed at developing a flexible, high-performance
hardware encryption core suitable for modern secure systems. The design supports 128-, 192-, and 256-bit key sizes and multiple
modes of operation including ECB, CBC, CFB, OFB, and CTR, enabling broad applicability across embedded and security-critical
platforms. The motivation behind this work is to address the growing need for efficient hardware-based encryption by replacing
software-heavy implementations with a compact and secure ASIC solution. The architecture integrates both encryption and
decryption within a unified core, reducing system complexity and improving integration efficiency. The project follows a structured
hardware design flow, starting from literature review and micro-architecture design to RTL implementation, UVM-based verification,
and synthesis, with layout considerations for ASIC deployment. Functional verification confirms correct AES operation and successful
single-core encryption/decryption capability across supported modes. The final design emphasizes modularity, scalability, and
compatibility with various key sizes, making it suitable for integration into secure embedded systems, processors, and SoCs. Overall,
this work demonstrates a practical understanding of hardware cryptography, digital IC design methodology, and end-to-end ASIC
development practices.
TECHNICAL EXPERTISE
Digital System Design & Processor Architecture
I design and implement complex digital systems using Hardware Description Languages (HDLs) like Verilog and SystemVerilog. My
core expertise lies in developing multi-stage pipelined architectures, where I architect data paths and control units to handle
instruction execution and hazard detection efficiently. ...

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