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Naeem Ullah

NUST · 2026

naeemullahullah29@gmail.com

Phone

923477967642

https://www.linkedin.com/in/naeem-ullah-a861a82a0/

GitHub

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Academic

Program

BS Electrical Engineering

CGPA

3.74

Year

2026

Education

SEECS, NUST

Address

P/O KAPAHI, DISTRICT BHAKKAR,TEHSIL MANKERA. , Bhakkar , Pakistan

DOB

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Career

Current role

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Target role

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Skills

C programming, Digital Logic Design, RISCV assembly, Computer Architecture, SystemVerilog, Verilog, RTL coding, Simulations, Hardware testing, PCB design, Layout optimization, SMD techniques, Hardware debugging, Validation, Micro- and nano-electronics, Embedded systems, Digital design, Advanced communication systems, IC design, 5G PHY layer, OpenAirInterface (OAI), SDR platform

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Naeem Ullah
Cell: 923477967642 | Email: naeemullahullah29@gmail.com
LinkedIn: https://www.linkedin.com/in/naeem-ullah-a861a82a0/
Address: P/O KAPAHI, DISTRICT BHAKKAR,TEHSIL MANKERA. , Bhakkar , Pakistan
PROFESSIONAL PROFILE
A passionate Electrical Engineering student at NUST with strong foundations in embedded
systems, digital design, and advanced communication systems. Experienced in hands-on
hardware development, IC design fundamentals, and practical engineering projects. Known for
problem-solving, teamwork, and the ability to learn and apply complex technical concepts quickly.
EDUCATION
Science
Govt. Model High School Bhakkar , Bhakkar , 1057/1100 (2020)
Pre-Engineering
Punjab Group Of Colleges (PGC) Bhakkar , Bhakkar , 1061/1100 (2022)
BS Electrical Engineering
SEECS, NUST , Islamabad , 3.74/4 (2026)
INTERNSHIP EXPERIENCE
Nust Chip Design Centre (NCDC)
05-Feb-2025 - 18-Jul-2025
Completed hands-on labs in C programming, Digital Logic Design, RISCV assembly, and Computer Architecture. Designed and
implemented a fully functional 5-stage pipelined RISCV processor in SystemVerilog, handling data, control, and structural hazards.
Developed a branch predictor module to improve processor performance and reduce control hazards. Gained experience with
industryrelevant IC design workflows, including design, simulation, and verification of digital systems.
System on Chip (SoC) Lab, SINES, NUST
18-Jul-2024 - 06-Sep-2024
Worked on processor design using Verilog/SystemVerilog. Performed RTL coding, simulations, and hardware testing. Successfully
implemented a digital design project demonstrating advanced logic and architecture concepts.
Micro and Nano Electronics (MiNE) Lab, RIMMS , NUST
05-Jun-2024 - 28-Aug-2024
Designed and developed PCB-proven electronic systems with emphasis on layout optimization and SMD techniques. Strengthened
practical knowledge of micro- and nano-electronics through real-world laboratory applications. Gained hands-on experience in
hardware debugging and validation.
FINAL YEAR PROJECT
5G Performance Optimization
Completed timing proﬁling of the 5G physical (PHY) layer to identify latency-critical processing blocks. Shifted selected time-critical
PHY functions from the Processing System (PS) to the Programmable Logic (PL). Working on real-time deployment of 5G New Radio
(NR) on an SDR platform using OpenAirInterface (OAI) 5g NR. Targeting improvement in system throughput and reduction in end-to-
end latency.
TECHNICAL EXPERTISE

AI enrichment

Naeem Ullah is a final-year BS Electrical Engineering student at NUST with a 3.74 CGPA, specializing in embedded systems, digital design, and IC development. He has gained practical experience through internships at NUST labs, including designing a pipelined RISC-V processor and working on 5G PHY layer optimization.

Skills (AI)

["SystemVerilog", "Verilog", "RISC-V", "Digital Logic Design", "PCB Design", "C Programming", "Embedded Systems", "5G NR", "OpenAirInterface", "Hardware Debugging"]

Status: ai_done

Provenance

Source file: SEECS - Electrical Engineering-2026.pdf
From job #259 page 48
Created: 1778168427