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Haseeb Umer

NUST · 2026

umerhaseeb96@gmail.com

Phone

923330669394

https://www.linkedin.com/in/haseebumer

GitHub

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Academic

Program

BE Electrical Engineering

CGPA

2.98

Year

2026

Education

School of Electrical Engineering and Computer Science

Address

Quetta, Pakistan

DOB

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Career

Current role

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Target role

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Skills

RTL design, functional verification, embedded systems, SystemVerilog, C/C++, Python, Makefile-based automation, RISC-V-DV, Spike, QuestaSim, RISC-V architecture, RV32IMCF, digital logic, peripheral interfacing, coverage-driven test planning, VLSI design, verification methodologies, embedded–hardware co-design, Vivado, Quartus, Cadence Xcelium, ModelSim, Verilator, Verilog, Assembly Language, finite state machines (FSMs), ALU development, datapath and control units, clock division, debouncing circuits, formal verification, test planning, assertion-based verification, GDB, Valgrind

Verbatim text

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Haseeb Umer
Cell: 923330669394 |  Email: umerhaseeb96@gmail.com
LinkedIn: https://www.linkedin.com/in/haseebumer
Address: HOUSE NO.105 KAFAYAT COLONY COMMAND AND STAFFCOLLEGE QUETTA CANTT , Quetta , Pakistan
PROFESSIONAL PROFILE
Final-year Electrical Engineering student with hands-on experience in RTL design, functional veriﬁcation, and embedded systems
development. Proﬁcient in SystemVerilog, C/C++, Python, and Makeﬁle-based automation for both hardware veriﬁcation and
ﬁrmware workﬂows. Experienced with RISC-V-DV, Spike, and QuestaSim for ISA-level and RTL-level veriﬁcation, along with STM32-
and ESP32-based microcontroller platforms for real-time embedded applications. Strong foundation in RISC-V architecture
(RV32IMCF), digital logic, peripheral interfacing, and coverage-driven test planning. Analytical and detail-oriented with a strong
passion for VLSI design, verification methodologies, and embedded–hardware co-design.
EDUCATION
BE Electrical Engineering
School of Electrical Engineering and Computer Science , Islamabad , 2.98 (2026)
INTERNSHIP EXPERIENCE
NUST Chip Design Centre
10-Feb-2025 - 29-Aug-2025
During my internship, I designed a 32-bit RISC-V processor datapath and control logic using SystemVerilog, where I implemented
complex FSM operations and register transfer logic. I ensured design reliability by achieving 100% functional coverage through
simulations in ModelSim and performed detailed timing and synthesis constraint analysis using Quartus and Vivado. Additionally, I
gained experience in the hardware-software interface by performing low-level debugging and memory analysis for C-based
embedded implementations using GDB and Valgrind, ensuring high-quality, stable code execution.
FINAL YEAR PROJECT
Performance Enhance Implementation of RISC-V Vector Extension
This project optimizes the RISC-V Vector (RVV) Extension to overcome performance bottlenecks in the vector core. By replacing
sequential processing with a multi-lane parallel architecture and optimizing the Load-Store Unit (LSU), we signiﬁcantly enhanced data
throughput for AI and DSP workloads. Following rigorous RTL veriﬁcation via QuestaSim and Verilator, the resulting high-
performance coprocessor maximizes data-level parallelism for modern, high-efficiency SoC environments.
TECHNICAL EXPERTISE
EDA & Simulation Tools
Hands-on experience with Vivado, Quartus, Cadence Xcelium, QuestaSim, ModelSim, and Verilator for synthesis, simulation, and
debugging.
Hardware Description Languages (HDLs)
Proficient in SystemVerilog, Verilog, and Assembly Language for digital design and low-level system implementation.
Digital System Design
Expertise in RTL design, ﬁnite state machines (FSMs), ALU development, datapath and control units, clock division, and debouncing
circuits.
Verification & Validation
Skilled in functional and formal verification, RISC-V DV flows, test planning, and assertion-based verification.

AI enrichment

Haseeb Umer is a final-year Electrical Engineering student specializing in RTL design, verification, and embedded systems with hands-on experience in RISC-V processor development. He has completed an internship at NUST Chip Design Centre and a final year project focused on optimizing the RISC-V Vector Extension for improved performance.

Skills (AI)

["SystemVerilog", "Verilog", "C/C++", "Python", "RISC-V Architecture", "RTL Design", "Functional Verification", "Embedded Systems", "Vivado", "Quartus", "QuestaSim", "ModelSim", "STM32", "ESP32", "Makefile", "GDB", "Verilator"]

Status: ai_done

Provenance

Source file: SEECS - Electrical Engineering-2026.pdf
From job #259 page 112
Created: 1778168427