Awais Asghar

Academic

Career

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Awais Asghar
Cell: 03267496818 |  Email: awaisasghara786@gmail.com
LinkedIn: https://www.linkedin.com/in/awais--asghar/
Address: NUST H-12 , Islamabad , Pakistan
PROFESSIONAL PROFILE
High-achieving Final Year Electrical Engineering student at NUST with specialized expertise in FPGA-based RTL Design,
Embedded Systems, and AI Acceleration. Proven track record in designing RISC-V Processors using SystemVerilog and
optimizing Deep Learning models for hardware integration. Selected for the prestigious MITACS Globalink Research Internship
(Canada, 2026), bringing diverse R&D experience in Chip Design and Embedded systems, aiming to deliver high-performance
solutions at the intersection of hardware and intelligent systems.
EDUCATION
Bachelor of Electrical Engineering
National University of Sciences and Technology (NUST) , Islamabad , 3.58/4.0 (2022 – 2026)
INTERNSHIP EXPERIENCE
NUST Chip Design Centre (NCDC)
12-Feb-2025 - 31-Aug-2025
Worked on FPGA-based digital chip design projects involving RTL design, simulation, and hardware implementation in System
Verilog, gaining hands-on experience with C programming, Linux, Digital System Design, RISC-V and computer architecture, and
processor design. Implemented a 5 Stage Pipelined Single-Cycle RISC-V Processor using System-Verilog on FPGA. Project includes
complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It
supports the complete RV32I instruction set (R, I, S, B, U, J types) and optimized for hardware-software co-design learning.
Designed and implemented an FPGA-based smart anti-theft car security system in Verilog HDL on the DE1-SoC, featuring a
reprogrammable FSM, sensor debouncing, siren generation, and a fuel-pump safety interlock to prevent unauthorized access.
Deep Learning Lab (SINES), NUST
01-Jun-2024 - 01-Sep-2024
Implemented machine learning and deep learning models for image processing and computer vision applications. Trained and
evaluated convolutional neural networks using PyTorch and TensorFlow with GPU acceleration through CUDA. Validated model
performance using standard metrics and gained experience in end to end model development and experimentation.
HamsanTech, NSTP
06-Jun-2023 - 01-Sep-2023
Built complete machine learning pipelines for industry datasets, covering data preprocessing, feature extraction, model training, and
evaluation. Developed a skin cancer detection system using ensemble learning techniques, achieving high classification accuracy
and strong AUC performance. Applied models including XGBoost, SVM, and Logistic Regression to deliver reliable and interpretable
results.
FINAL YEAR PROJECT
ML based Hardware Accelerator for Real Time Image Segmentation on FPGA
Designing an FPGA based hardware accelerator for real time image segmentation using an encoder decoder architecture. The
project focuses on deploying a lightweight U-Net model optimized for hardware implementation to achieve low latency and high
throughput. Parallel processing and on chip memory optimization techniques are used to efficiently map convolution, pooling, and
upsampling operations on FPGA fabric. The system is evaluated by benchmarking performance against CPU and GPU
implementations in terms of speed, accuracy, and energy efficiency, with target applications in autonomous driving and medical
imaging.

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