Muhammad Abdullah
NUST
· 2026
Email
abdullzaheer43@gmail.com
Phone
03102995649
GitHub
—
Academic
Program
BSE
CGPA
3.24
Year
2026
Education
SEECS
Address
Islamabad
DOB
—
Career
Current role
—
Target role
—
Skills
RISC-V architecture, embedded systems, machine learning, computer vision, RISC-V assembly, computer architecture, FPGA design, SystemVerilog, Python, TensorFlow, Verilog, Arduino, ATmega, SPI protocol, Digital Logic Design, C language
Verbatim text
The exact text the LLM saw on the page (or the booklet text from the old import).
This is what powers semantic search.
Muhammad Abdullah Cell: 03102995649 | Email: abdullzaheer43@gmail.com LinkedIn: https://www.linkedin.com/in/abdullah-zaheer-263b63312? utm_source=share&utm_campaign=share_via&utm_content=profile&utm_medium=ios_app Address: Nust , H-12 , Islamabad , Pakistan PROFESSIONAL PROFILE Final-year Electrical Engineering student at NUST with strong expertise in RISC-V architecture, embedded systems, and machine learning–based applications. Hands-on experience in RISC-V assembly, computer architecture, FPGA design, and SystemVerilog, along with practical exposure to machine learning and computer vision for intelligent systems. Proven ability to integrate hardware and software through academic projects and chip design training. Seeking opportunities to contribute to cutting-edge embedded, AI, and hardware-accelerated computing solutions. EDUCATION Bachelor of Electrical Engineering School of Electrical Engineering and Computer Science , Islamabad , 3.24 (2026) INTERNSHIP EXPERIENCE NCDC, Islamabad 19-Feb-2025 - 10-Jun-2025 Trainee -Worked on chip design, C language, DLD concepts, RiscV Assembly and System Verilog NUST Chip Design Centre 10-Jun-2025 - 29-Aug-2025 - Contributed to a RISC-V Vector Extension (RVV)–based SoC template design, focusing on processor architecture, vector execution flow, and hardware software interaction. - Developed and analyzed RISC-V assembly programs to validate architectural behavior and instruction-level execution. - Applied Digital Logic Design and Computer Architecture concepts to implement and verify RTL modules using SystemVerilog, supporting SoC integration and functional correctness. FINAL YEAR PROJECT Design and Verification of RISC-V Vector Processor IP Designing and verifying a RISC-V Vector Processor IP based on the RISC-V Vector Extension (RVV). Implementing vector execution units and control logic using SystemVerilog, with functional verification through simulation and testbenches to ensure correctness and compliance with the RISC-V specification. TECHNICAL EXPERTISE Machine Learning & Computer Vision Projects Academic & Certified Projects - Developed ML-based systems using Python and TensorFlow for intelligent control and automation tasks. - Implemented computer vision pipelines for object detection and tracking in embedded applications. - Integrated ML/CV models with hardware systems for real-time decision-m ... Embedded Systems & FPGA Projects Academic Projects - Implemented SPI protocol on FPGA using Verilog/SystemVerilog and verified functionality via simulation. - Designed embedded systems using microcontrollers (Arduino, ATmega) for automation and control applications. - Integrated sensors and control algorithms for real-time system respon ... Chip Design & Computer Architecture Trainee
AI enrichment
Muhammad Abdullah is a final-year Electrical Engineering student specializing in RISC-V architecture, embedded systems, and chip design. He has practical experience through internships at NCDC and the NUST Chip Design Centre, focusing on SystemVerilog, FPGA development, and RISC-V Vector Extension implementations.
Skills (AI)
["RISC-V Architecture", "SystemVerilog", "FPGA Design", "Embedded Systems", "Machine Learning", "Computer Vision", "Python", "TensorFlow", "Digital Logic Design", "Computer Architecture", "C Language", "Verilog", "Microcontrollers"]
Status: ai_done
Provenance
Source file: SEECS - Electrical Engineering-2026.pdfFrom job #259 page 216
Created: 1778168428