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Sataish Elahi

NUST · 2026

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Phone

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GitHub

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Academic

Program

BEE

CGPA

3.53

Year

2026

Education

SEECS

Address

607-N-SAMNABAD , Pakistan

DOB

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Career

Current role

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Target role

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Skills

C, C++, Python, RISC-V Assembly, Verilog, SystemVerilog, MATLAB, Vivado, Quartus Prime, ModelSim, Xilinx Xcelium, PlatformIO IDE, Proteus, PSpice, LTSpice, Simscape Multibody, Mbed Studio, Verilator, digital system design, computer architecture, FPGA-based development, embedded systems, hardware design, verification, system integration

Verbatim text

The exact text the LLM saw on the page (or the booklet text from the old import). This is what powers semantic search.

Sataish Elahi
Cell: | Email:
Address: 607-N-SAMNABAD , Pakistan
PROFESSIONAL PROFILE
Electrical Engineering undergraduate from NUST with strong interests in digital system design, computer architecture, FPGA-based
development, and embedded systems. Experienced in designing pipelined RISC-V processors, FSM-based hardware systems, and
simulation-driven engineering projects. Seeking graduate-level opportunities to apply hardware design, veriﬁcation, and system
integration skills in research or industry-focused engineering roles.
EDUCATION
Bachelor of Electrical Engineering
School of Electrical Engineering and Computer Science , Islamabad , 3.53 (2026)
INTERNSHIP EXPERIENCE
NUST Chip Design Centre
23-Feb-2025 - 29-Aug-2025
Designed and implemented an FSM-based anti-theft car system on FPGA using SystemVerilog in Vivado, with emphasis on reliable
state transitions and real-time operation. Developed a 32-bit RV32I RISC-V processor core featuring a ﬁve-stage pipelined
architecture with data and control hazard detection and resolution. Integrated instruction memory, data memory, and peripheral
modules using the Wishbone bus to enable complete SoC-level functionality. Veriﬁed system correctness through simulation,
waveform analysis, and comprehensive testbenches.
FINAL YEAR PROJECT
Performance Enhanced RISC-V Vector Processor
The project involves upgrading an existing RISC-V processor implementation by designing and integrating a vector coprocessor to
accelerate data-parallel computations. It focuses on enhancing performance through improved vector execution support while
maintaining compatibility with the base RISC-V architecture. The work includes architectural modiﬁcations, coprocessor integration,
and optimization of vector operations. Performance evaluation is carried out using simulation and benchmarking to assess speedup,
efficiency, and scalability.
TECHNICAL EXPERTISE
Programming & Hardware Description Languages
C, C++, Python, RISC-V Assembly, Verilog, SystemVerilog, MATLAB
Design and Simulation Tools
Vivado, Quartus Prime, ModelSim, Xilinx Xcelium, PlatformIO IDE, Proteus, PSpice, LTSpice, Simscape Multibody, Mbed Studio,
Verilator

AI enrichment

Sataish Elahi is an Electrical Engineering undergraduate at NUST with a 3.53 CGPA, specializing in digital system design, FPGA development, and embedded systems. He has practical experience designing pipelined RISC-V processors and FSM-based hardware systems through internship and academic projects.

Skills (AI)

["SystemVerilog", "Verilog", "RISC-V", "FPGA Development", "Vivado", "Embedded Systems", "C", "C++", "Python", "Digital Logic Design", "Simulation", "Computer Architecture"]

Status: ai_done

Provenance

Source file: SEECS - Electrical Engineering-2026.pdf
From job #259 page 165
Created: 1778171329