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Mian Tahir Nadeem

NUST · 2026 · 407752
Email
mnadeem.bee22seecs@seecs.edu.pk
Phone
923411623120
LinkedIn
https://www.linkedin.com/in/mian-tahir-nadeem-b13a0a2b7
GitHub

Academic

Program
CGPA
3.77
Year
2026
Education
Bachelor of Electrical Engineering School of Electrical Engineering and Computer Science (SEECS) NUST , Islamabad , 3.77 (2026)
Address
POST OFFICE KHAS KALYANA PAKAPATTAN , Lahore , Pakistan
DOB

Career

Current role
Target role
Skills
PROFESSIONAL PROFILE Highly motivated Electrical Engineering undergraduate at NUST with strong academic standing (CGPA 3.77/4.0) and hands-on experience in Analog, RF, and Mixed-Signal IC Design. Currently working on a wideband tunable Variable Gain Amplifier (7–24 GHz) for 6G transmitter front-ends, with practical exposure to Cadence Virtuoso, schematic design, layout, and post-layout verification. Research-oriented candidate with experience in wireless communication systems, RIS-assisted networks, and deep learning with strong analytical skills, circuit design expertise, and research aptitude. EDUCATION Bachelor of Electrical Engineering School of Electrical Engineering and Computer Science (SEECS) NUST , Islamabad , 3.77 (2026) INTERNSHIP EXPERIENCE Deep Learning Lab, SEECS-NUST 01-Jun-2023 - 02-Sep-2023 Worked on automated image classification using deep learning techniques. Achieved improved accuracy compared to classical machine learning methods such as Support Vector Machines (SVMs). Contributed to data preprocessing, model training, and performance evaluation. Information Processing & Transmission Lab (IPT), SEECS-NUST 09-May-2024 - 07-Sep-2024 Conducted research on Non-Orthogonal Multiple Access (NOMA) and Orthogonal Multiple Access (OMA) techniques for next- generation wireless systems. Investigated Reconfigurable Intelligent Surfaces (RIS) to enhance spectral efficiency and system capacity. Assisted in simulation, performance evaluation, and documentation of RIS-assisted communication models, contributing to lab reports and ongoing publications NUST Chip Design Centre (NCDC), SINES – Islamabad 01-Jan-2025 - 27-Jan-2026 Completed intensive training in Analog and Mixed-Signal IC Design covering MOSFET physics, current mirrors, differential amplifiers, frequency response analysis, bandgap references, OTAs, oscillators, PLLs, and comparators. Designed, simulated, and verified multiple analog building blocks using Cadence Virtuoso (65 nm PDK). Performed layout design and post-layout simulations for single- stage amplifiers and Operational Transconductance Amplifiers (OTAs). Gained practical understanding of IC fabrication flow and layout-level performance trade-offs. FINAL YEAR PROJECT Wideband Tunable Variable Gain Amplifier (7–24 GHz) for Phased-Array Based 6G Transmitter Front-End Designing a wideband, tunable Variable Gain Amplifier (VGA) operating from 7–24 GHz, targeting FR3 and emerging 6G frequency bands. The project is conducted as part of a collaborative research initiative between NUST and King Abdullah University of Science and Technology (KAUST), focusing on phased-array transmitter architectures for next-generation wireless systems. The VGA is intended to function as a core building block in phased-array front-ends, enabling element-level gain control essential for beam steering, beamforming, and array calibration. Emphasis was placed on adaptive gain control, high linearity, low noise performance, and wideband impedance matching, ensuring robustness across multi-band phased-array operation. Objective: complete schematic

AI enrichment

Highly motivated Electrical Engineering undergraduate at NUST with strong academic standing (CGPA 3.77/4.0) and hands-on experience in Analog, RF, and Mixed-Signal IC Design. Currently working on a wideband tunable Variable Gain Amplifier (7–24 GHz) for 6G transmitter front-ends, with practical exposure to Cadence Virtuoso, schematic design, layout, and post-layout verification. Research-oriented candidate with experience in wireless communication systems, RIS-assisted networks, and deep learning with strong analytical skills, circuit design expertise, and research aptitude.
Status: ai_done
Provenance
Source file:
Created: 1777448793