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Khansa Mishqat

NUST · 2026 · 416793
Email
kmishqat.bee22seecs@seecs.edu.pk
Phone
923185437479
LinkedIn
https://www.linkedin.com/in/khansa-mishqat-30bb8b275
GitHub

Academic

Program
CGPA
3.02
Year
2026
Education
Bachelor of Electrical Engineering SEECS , Islamabad , 3.02 (2026)
Address
HOUSE NO.575-B, SECTOR G-7/3-1, ISLAMABAD-44000 , Islamabad , Pakistan
DOB

Career

Current role
Target role
Skills
PROFESSIONAL PROFILE Final-year Electrical Engineering student at NUST with a specialized focus on Digital System Design, Embedded Systems, and AI Hardware Acceleration. Gained industry experience during a research internship at NECOP, where i in a team designed and modified AXI/DMA-based data transfer systems and custom control logic on FPGA. Currently working on a high-speed AI accelerator for YOLOv8 inference on the Xilinx ZCU102 platform to optimize real-time latency and throughput. Proficient in languages like Verilog/SystemVerilog, Python, C++ and Assembly and tools like Vivado, Quartus, Matlab, Pspice and Proteus, with a strong interest in edge AI and secure hardware architecture. EDUCATION Bachelor of Electrical Engineering SEECS , Islamabad , 3.02 (2026) INTERNSHIP EXPERIENCE NECOP 23-Jun-2025 - 23-Sep-2025 The key higlights of my internship were: 1. Studied modern hardware accelerator architectures to understand how computation and data movement are designed together. 2. Worked with a DMA loopback–based accelerator design and learned how data is transferred between the Processing System (PS) and Programmable Logic (PL) using AXI interfaces. 3. Modified the design to support two input streams and added buffers inside the processing loop, controlled from the PS side, to manage data flow. FINAL YEAR PROJECT High Speed AI Accelerator on FPGA for Real-Time Object Detection Designed and implemented an FPGA-based AI accelerator for real-time object detection and classification, using custom hardware IPs to speed up the compute-heavy parts of a YOLO-based model while the processing system manages control and integration. The system is built in a modular way with clear PS–PL communication, keeping the overall design simple and extendable. TECHNICAL EXPERTISE FPGA & Digital Systems Design Verilog, SystemVerilog, Vivado, Vitis, Quartus, ModelSim, RISC-V, AXI Protocol. Programming C/C++, Python and Assembly Embedded Systems Embedded C, Microcontroller Programming, GPIO & Peripheral Interfacing, I2C, SPI, UART Microcontrollers: Arduino, ATmega328P, ATmega16A, STM32, ESP32 Tools: Arduino IDE, Atmel Studio, STM32CubeIDE Machine Learning Data Cleaning & Preprocessing, Feature Extraction, Supervised & Unsupervised Learning, Linear & Logistic Regression, Decision Trees, SVM, K-Nearest Neighbors, Clustering, Dimensionality Reduction (PCA)

AI enrichment

Final-year Electrical Engineering student at NUST with a specialized focus on Digital System Design, Embedded Systems, and AI Hardware Acceleration. Gained industry experience during a research internship at NECOP, where i in a team designed and modified AXI/DMA-based data transfer systems and custom control logic on FPGA. Currently working on a high-speed AI accelerator for YOLOv8 inference on the Xilinx ZCU102 platform to optimize real-time latency and throughput. Proficient in languages like Verilog/SystemVerilog, Python, C++ and Assembly and tools like Vivado, Quartus, Matlab, Pspice and Proteus, with a strong interest in edge AI and secure hardware architecture.
Status: ai_done
Provenance
Source file:
Created: 1777448793