Ahmed Jamil
NUST
· 2026
·
403420
Email
ajamil.bee22seecs@seecs.edu.pk
Phone
923246106402
GitHub
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Academic
Program
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CGPA
3.28
Year
2026
Education
BEE (Electrical Engineering)
School of Electrical Engineering and Computer Sciences (SEECS) , Islamabad , 3.3 (4)
Address
HS#2,ST#5,BAZAR #1 ASGHAR COLONY NEARNIGAR UNDERPASS ,FAISAL ROAD , Gujranwala , Pakistan
DOB
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Career
Current role
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Target role
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Skills
PROFESSIONAL PROFILE
Electrical Engineer specializing in embedded systems and semiconductor design, with hands-on experience in chip design and
verification. Strong focus on applying AI techniques within embedded environments to build efficient, intelligent, and hardware-aware
solutions.
EDUCATION
BEE (Electrical Engineering)
School of Electrical Engineering and Computer Sciences (SEECS) , Islamabad , 3.3 (4)
INTERNSHIP EXPERIENCE
ChipXprt
09-Jun-2025 - 11-Jul-2025
Worked on the processor core design and Verification
System On Chips (SoC) Lab
14-Jul-2025 - 22-May-2026
Working on Risc - V Neuromorphic Accelerator for Low power Surveillance.
FINAL YEAR PROJECT
Risc V Based Neuromorphic Accelerator for Spiking Neural Networks
This project focuses on the design and implementation of a RISC-V based neuromorphic accelerator specifically optimized for Spiking
Neural Networks (SNNs). Spiking neural networks are inspired by the way biological neurons communicate using discrete spikes,
making them highly energy-efficient and suitable for real-time and edge-based intelligent systems. The proposed system integrates a
lightweight RISC-V processor with a custom neuromorphic accelerator to efficiently handle spike-based computation, neuron
updates, and synaptic weight processing. While the RISC-V core manages control flow and general operations, the accelerator is
responsible for parallel spike processing, reducing execution latency and power consumption compared to conventional CPU-based
implementations. The project explores neuron models, spike encoding, and event-driven computation, and evaluates the system in
terms of performance, scalability, and energy efficiency. The final implementation can be validated through simulation and/or FPGA
prototyping, demonstrating how open-source RISC-V architectures can be extended for emerging AI workloads such as
neuromorphic computing. This work highlights the potential of combining open-source hardware with brain-inspired computing to
build efficient and adaptable AI accelerators for future embedded and edge applications.
TECHNICAL EXPERTISE
Vivado
Proficient in using Xilinx Vivado for FPGA design, synthesis, implementation, and timing analysis. Experienced in developing and
debugging Verilog/SystemVerilog designs, integrating IP cores, running simulations, and generating bitstreams for FPGA-based
prototyping and validation.
Verilator
Hands-on experience using Verilator for high-speed simulation and verification of SystemVerilog and Verilog designs. Skilled in
converting RTL designs into cycle-accurate C++ models for functional validation, performance analysis, and debugging of hardware
modules. Familiar with testbench integration, wavefor ...
AI enrichment
Electrical Engineer specializing in embedded systems and semiconductor design, with hands-on experience in chip design and
verification. Strong focus on applying AI techniques within embedded environments to build efficient, intelligent, and hardware-aware
solutions.
Status: ai_done
Provenance
Source file: —Created: 1777448793