Aized Soban

PROFESSIONAL PROFILE Electrical Engineering undergraduate with hands-on experience in digital design, RISC-V processor architectures, and hardware verification. Currently working part-time at Xcelerium (since Nov 2025) on CVA6 core instruction tracing and UVM-based logic trace verification, with exposure to real-world RTL debugging and verification workflows. Previously trained at National Chip Design Centre (NCDC), NUST, where I designed and verified a 5-stage pipelined RISC-V processor and worked on cache architectures, hazard resolution, and SystemVerilog testbenches. Strong interest in semiconductor design, processor microarchitecture EDUCATION BEE SEECS , Islamabad , 3.28 (2022) INTERNSHIP EXPERIENCE Xcelerium | Nov 2025 – Present 01-Nov-2025 - 25-Jan-2026 Part-Time Hardware Verification Engineer Working on instruction-level and logic trace verification for the CVA6 RISC-V core. Integrating and analyzing execution traces to validate core behavior against expected instruction flow. Developing and executing UVM-based verification tasks focused on trace correctness and corner cases. Debugging RTL and simulation mismatches using waveform analysis and trace comparison. Gaining hands-on exposure to industry-grade verification workflows and large-scale RTL codebases. Nust Chip Design Centre (NCDC) 01-Feb-2025 - 31-Aug-2025 Intern Trainee – Digital Systems & RISC-V Architecture Designed and verified a 5-stage pipelined RISC-V processor supporting RISBUJ instruction formats. Implemented pipeline hazard handling including data forwarding, stalling, and branch control. Developed SystemVerilog testbenches and performed functional verification using ModelSim. Studied cache memory organizations (direct- mapped, set-associative) and performance trade-offs. Contributed to architectural exploration for a dual-core SMP processor with MESI-based cache coherence as part of an ASIC tape-out track. FINAL YEAR PROJECT ASIC Tape-out of Dual-Core SMP RISC-V Processor with MESI-Based Cache Coherence Working on the architectural design and simulation of a dual-core symmetric multiprocessing (SMP) RISC-V processor targeting ASIC tape-out. Developing a cache hierarchy implementing the MESI coherence protocol to ensure correct shared-memory operation across cores. Using gem5 for architectural simulation and performance evaluation under parallel workloads. Analyzing interconnect design, coherence controllers, and memory access behavior. Evaluating system-level performance trade-offs related to cache organization, coherence traffic, and scalability. TECHNICAL EXPERTISE Digital Design & Hardware Verification Hands-on experience in RISC-V processor design and verification, including pipelined microarchitectures, hazard resolution, and cache subsystem concepts. Actively working on instruction and logic trace verification for the CVA6 core using UVM methodologies, with strong exposure to RTL debugging and waveform-b ...

Electrical Engineering undergraduate with hands-on experience in digital design, RISC-V processor architectures, and hardware verification. Currently working part-time at Xcelerium (since Nov 2025) on CVA6 core instruction tracing and UVM-based logic trace verification, with exposure to real-world RTL debugging and verification workflows. Previously trained at National Chip Design Centre (NCDC), NUST, where I designed and verified a 5-stage pipelined RISC-V processor and worked on cache architectures, hazard resolution, and SystemVerilog testbenches. Strong interest in semiconductor design, processor microarchitecture