Abdullah Mir

PROFESSIONAL PROFILE Embedded Systems and Digital Design enthusiast with hands-on experience in C/C++, microcontrollers (STM32, ESP32, Arduino), and FPGA-based hardware accelerators. Worked on post-quantum cryptography (ASCON) accelerators, CPU design in SystemVerilog, and real-time embedded projects using sensors and communication protocols. Strong in self-learning, documentation, and explaining complex concepts to others. EDUCATION Electrical engineering seecs , Islamabad , 3.0 (2022) INTERNSHIP EXPERIENCE SOC lab/Nstp/NUSt 01-Apr-2025 - 14-Jan-2026 • Worked on hardware accelerators for PQC (ASCON-128), focusing on side-channel resistance and secure hardware for embedded systems. • Verified ASCON in C using NIST vectors and integrated with FPGA flow (Vivado/Quartus). • Designed simple CPU in SystemVerilog (ALU, regfile, decoder, control), verified via RTL simulation & synthesis. • Exposure to ASIC flow – floorplanning, STA, PPA trade-offs. • Performed literature review and contributed to research publication. SDAC, Embedded Systems Research Lab – NUST 01-Jun-2024 - 01-Aug-2024 • Built FPGA-based solutions on DE1-SoC integrating ARM Cortex-A9 with custom logic for embedded applications. • Developed Linux kernel modules/character drivers for custom peripherals using file ops & ioctl. • Interfaced sensors & peripherals using C/C++ with interrupts, polling, and MMIO. • Worked with UART, SPI, I2C; debugged using logs & test utilities. QKZEE Technologies 01-Apr-2023 - 01-Sep-2023 • Assembled and tested electronic circuits using soldering, PCB design workflows, and Proteus simulations, supporting academic and IoT-based hardware projects. • Developed microcontroller-based prototypes on Arduino, ESP32, and Raspberry Pi, integrating ultrasonic, IR, temperature, humidity, gas, and motion sensors. • Implemented power regulation and switching circuits using MOSFETs, BJTs, voltage regulators, capacitors, and batteries ensuring safe and stable device operation. • Debugged hardware issues including noisy signals, incorrect pin mapping, unstable power, and coding errors. FINAL YEAR PROJECT sharp: secure hardware accelerator for post quantum cryptography algorithms This Final Year Project focuses on the design and implementation of SHARP (Secure Hardware Accelerator for Post-Quantum Cryptography), a dedicated cryptographic accelerator targeting ASCON-128a, a NIST-standardized lightweight post-quantum cryptographic algorithm. The objective of SHARP is to enable secure, efficient, and side-channel-resistant communication for resource-constrained IoT and embedded systems in the post-quantum era. The project explores and evaluates three architectural approaches for ASCON-128a implementation: single-cycle, multi-cycle, and pipelined architectures, with a detailed analysis of power, performance, and area (PPA) trade-offs. Based on these evaluations, a potential hybrid architecture is being investigated to further optimize efficiency while maintaining security guarantees. A strong emphasis is placed on hardware-level side-channel resistance, ensuring robustness against physical attacks such as power analysis. The final deliverable is a synthesizable chip-level design suitable for integration into IoT platforms, enabling secure communication in the quantum computing era. Currently, the SHARP

Embedded Systems and Digital Design enthusiast with hands-on experience in C/C++, microcontrollers (STM32, ESP32, Arduino), and FPGA-based hardware accelerators. Worked on post-quantum cryptography (ASCON) accelerators, CPU design in SystemVerilog, and real-time embedded projects using sensors and communication protocols. Strong in self-learning, documentation, and explaining complex concepts to others.