Haseeb Umer

PROFESSIONAL PROFILE Final-year Electrical Engineering student with hands-on experience in RTL design, functional verification, and embedded systems development. Proficient in SystemVerilog, C/C++, Python, and Makefile-based automation for both hardware verification and firmware workflows. Experienced with RISC-V-DV, Spike, and QuestaSim for ISA-level and RTL-level verification, along with STM32- and ESP32-based microcontroller platforms for real-time embedded applications. Strong foundation in RISC-V architecture (RV32IMCF), digital logic, peripheral interfacing, and coverage-driven test planning. Analytical and detail-oriented with a strong passion for VLSI design, verification methodologies, and embedded–hardware co-design. EDUCATION BE Electrical Engineering School of Electrical Engineering and Computer Science , Islamabad , 2.98 (2026) INTERNSHIP EXPERIENCE NUST Chip Design Centre 10-Feb-2025 - 29-Aug-2025 During my internship, I designed a 32-bit RISC-V processor datapath and control logic using SystemVerilog, where I implemented complex FSM operations and register transfer logic. I ensured design reliability by achieving 100% functional coverage through simulations in ModelSim and performed detailed timing and synthesis constraint analysis using Quartus and Vivado. Additionally, I gained experience in the hardware-software interface by performing low-level debugging and memory analysis for C-based embedded implementations using GDB and Valgrind, ensuring high-quality, stable code execution. FINAL YEAR PROJECT Performance Enhance Implementation of RISC-V Vector Extension This project optimizes the RISC-V Vector (RVV) Extension to overcome performance bottlenecks in the vector core. By replacing sequential processing with a multi-lane parallel architecture and optimizing the Load-Store Unit (LSU), we significantly enhanced data throughput for AI and DSP workloads. Following rigorous RTL verification via QuestaSim and Verilator, the resulting high- performance coprocessor maximizes data-level parallelism for modern, high-efficiency SoC environments. TECHNICAL EXPERTISE EDA & Simulation Tools Hands-on experience with Vivado, Quartus, Cadence Xcelium, QuestaSim, ModelSim, and Verilator for synthesis, simulation, and debugging. Hardware Description Languages (HDLs) Proficient in SystemVerilog, Verilog, and Assembly Language for digital design and low-level system implementation. Digital System Design Expertise in RTL design, finite state machines (FSMs), ALU development, datapath and control units, clock division, and debouncing circuits. Verification & Validation Skilled in functional and formal verification, RISC-V DV flows, test planning, and assertion-based verification.

Final-year Electrical Engineering student with hands-on experience in RTL design, functional verification, and embedded systems development. Proficient in SystemVerilog, C/C++, Python, and Makefile-based automation for both hardware verification and firmware workflows. Experienced with RISC-V-DV, Spike, and QuestaSim for ISA-level and RTL-level verification, along with STM32- and ESP32-based microcontroller platforms for real-time embedded applications. Strong foundation in RISC-V architecture (RV32IMCF), digital logic, peripheral interfacing, and coverage-driven test planning. Analytical and detail-oriented with a strong passion for VLSI design, verification methodologies, and embedded–hardware co-design.