Hasan Ahmad

PROFESSIONAL PROFILE Electrical Engineering undergraduate with a strong focus on Digital Logic Design, RTL, and Embedded Systems. Proficient in Verilog and FPGA implementation, with a deep understanding of Computer Architecture. Innovative problem solver currently leading the development of an AI-powered tool to automate UVM testbench generation, bridging the gap between natural language processing and hardware verification. EDUCATION Bachelor of Engineering in Electrical Engineering (B.E. EE) School of Electrical Engineering and Computer Science (SEECS) , Islamabad , 3.95/4.00 (2026) INTERNSHIP EXPERIENCE National Electronics Complex Of Pakistan (NECOP) 24-Jun-2025 - 23-Sep-2025 • Conducted research and literature review on indigenous FPGA architectures and development flows, gaining hands-on experience with the OpenFPGA toolchain. • Designed, simulated, and debugged 250+ digital circuits using Verilog/SystemVerilog, leveraging AMD Vivado and Cadence Xcelium, subsequently generating configuration bitstreams for hardware testing. • Analysed FPGA netlists and architectural constraints to investigate and resolve configuration and bitstream mismatches. • Designed and implemented an RTL-based JTAG interface from scratch; simulated, integrated, and validated it within the top-level FPGA design in Vivado. • Worked closely with verification teams to validate FPGA designs and improve design–verification integration workflows. Pakistan Ministry of Railways 29-Jul-2024 - 12-Aug-2024 • Gained practical exposure to electrical subsystems in diesel-electric train engines, including control panels, power distribution, and engine room operations. • Observed maintenance, testing, and fault diagnosis procedures across multiple departments, developing an understanding of large-scale electrical systems and operational constraints. M-Labs (Mindstorm Studios) 07-Jun-2024 - 12-Aug-2024 • Contributed to a small team-based software development project using C# within the Unity environment, gaining experience in collaborative development workflows and rapid prototyping. Systems Limited 19-Jun-2023 - 25-Jul-2023 • Supported internal IT operations by configuring and maintaining employee workstations and resolving day-to-day technical issues in a corporate environment. FINAL YEAR PROJECT VeriLLM: LLM-Accelerated UVM Testbench Development Designing and building VeriLLM, a system that bridges the gap between Generative AI and Hardware Verification. Addressed the industry bottleneck of time-consuming boilerplate code by creating a tool that accepts natural language specifications and outputs complete, compile-ready UVM class hierarchies. The system aims to successfully automate the creation of components like APB monitors and drivers, demonstrating the potential of LLMs to accelerate digital design verification workflows.

Electrical Engineering undergraduate with a strong focus on Digital Logic Design, RTL, and Embedded Systems. Proficient in Verilog and FPGA implementation, with a deep understanding of Computer Architecture. Innovative problem solver currently leading the development of an AI-powered tool to automate UVM testbench generation, bridging the gap between natural language processing and hardware verification.