Muhammad Arham Siddiqui

PROFESSIONAL PROFILE Electrical Engineering undergraduate at NUST SEECS with a 3.92 CGPA and a focus on System-on-Chip design and Computer Architecture. My background combines industry experience in hardware verification from DreamBig Semiconductors with academic research in AI for Electronic Design Automation. Currently, I am leading research on using Large Language Models to automate UVM testbench generation while finalizing my degree. I have practical experience with AMBA protocols, RTL design, and SystemVerilog, and I am looking to apply these skills in a challenging digital IC design or verification role. EDUCATION BE Electrical Engineering School of Electrical Engineering and Computer Science , Islamabad , 3.90 (2026) INTERNSHIP EXPERIENCE DreamBig Semiconductors 01-Jun-2025 - 31-Aug-2025 During my internship at DreamBig Semiconductors, I focused on developing UVM-based verification environments for AMBA protocol IPs. I was responsible for implementing essential components including agents, drivers, monitors, and scoreboards to support complex SoC subsystems. My daily work involved waveform debugging, running protocol compliance checks, and managing regressions to ensure verification quality. I also collaborated closely with senior engineers on structured verification planning and achieving coverage closure. NUST Chip Design Center 01-Feb-2025 - 31-May-2025 I worked as a Digital IC Design Intern where I designed, simulated, and verified RTL modules using Verilog and SystemVerilog. I assisted the team with FPGA prototyping, including pin planning and timing validation, and helped integrate custom IP blocks into larger designs. Additionally, I conducted block-level functional testing and validated pipeline behavior to support the lab's VLSI design flows and hardware validation processes. FINAL YEAR PROJECT VeriLLM: LLM-Accelerated UVM Testbench Development As the technical lead at the System on Chip Lab, I am directing the development of an AI driven framework designed to automate the creation of UVM verification environments. This project addresses the increasing complexity of modern IC designs by translating natural language specifications into fully synthesizable SystemVerilog code. In this role, I manage a team of three researchers and oversee the project roadmap, which included building a custom dataset generation pipeline to better train our models on UVM structures. My technical contributions involve designing system architectures and abstraction models that enable Large Language Models to autonomously generate essential testbench components such as agents, drivers, and scoreboards. Beyond code generation, the project investigates how to integrate LLM reasoning with formal verification and coverage guided stimulus generation to improve overall design assurance. We have successfully developed a prototype that produces syntactically correct SystemVerilog components and are currently preparing our findings for publication. TECHNICAL EXPERTISE Hardware Verification & UVM Methodology My core experience lies in developing UVM-based verification environments, specifically for AMBA protocol IPs. During my time at

Electrical Engineering undergraduate at NUST SEECS with a 3.92 CGPA and a focus on System-on-Chip design and Computer Architecture. My background combines industry experience in hardware verification from DreamBig Semiconductors with academic research in AI for Electronic Design Automation. Currently, I am leading research on using Large Language Models to automate UVM testbench generation while finalizing my degree. I have practical experience with AMBA protocols, RTL design, and SystemVerilog, and I am looking to apply these skills in a challenging digital IC design or verification role.