Abdul Hannan Adil

PROFESSIONAL PROFILE Electrical Engineering undergraduate with strong hands-on experience in processor microarchitecture, FPGA-based system design, and hardware implementation of cryptographic algorithms. Proven capability in designing and verifying RISC-V processors (single- cycle and pipelined), integrating SoC components, and developing secure hardware accelerators for post-quantum IoT applications. Currently serving as an Undergraduate Research Assistant, working on high-performance, area-efficient implementations of Post Quantum Cryptographic Algorithm with a focus on throughput optimization and side-channel security. Demonstrates practical problem-solving ability, continuous learning, and a research-driven approach to digital system and processor-level security design. To continue my passion and contribute to open source, I have a Github repository, below is my attached Github Repositry. https://github.com/abdulhannanadil EDUCATION BE Electrical & Electronics Engineering SEECS , Islamabad (2026) INTERNSHIP EXPERIENCE LT Engineering 12-Aug-2024 - 12-Sep-2025 During my 4 weeks internship at LT Engineering, Fiber-Optic Cable Manufacturing Company, I learned following things: 1. Harnessing and lathing its importance and how it's done. 2. Fiber Optical Cable Manufacturing 3. Fiber Testing 4. HVAC Systems Research Assistant at Systems on Chip Lab 01-Jul-2025 - 01-Jun-2026 As a research assistant I am currently working and researching on: - Post Quantum Cryptographic Algorithm for IoT - Implementation of Hardware Accelerator for Post Quantum Cryptographic Algorithm for IoT - Making the Hardware Accelerator secure from Side Channel Attacks FINAL YEAR PROJECT Ascon - 128 Cryptographic Engine on STM 32 Tools: Embedded C, STM32CubeIDE, STM32F429 - Implemented the Ascon -128 A authenticated encryption algorithm in C and ported it to an STM32F429 microcontroller - Adapted the reference implementation for embedded constraints, focusing on memory efficiency and execution correctness - Integrated encryption and decryption routines with on-board peripherals to demonstrate real- time operation - Validated functional correctness through test vectors and live input/output visualization on the LCD interface - Analyzed execution behavior and resource usage to ensure suitability for constrained embedded environments Digital Twin Based Side-Channel Attack Prediction System using CNN In this project, I created a digital twin environment for obtaining, the Realtime dataset for Side Channel Attack. For this we used Rainbow Side Channel Attack prediction software, linked it with our Ascon - 128 A implementations, and created a digital twin to recover the key. If the key was recovered it was assigned a zero label and if it was unable to recover the key it was assigned one. Then using the CNN, we predicted that the given code is Side Channel Attack resistant or not. Secure Hardware Accelerator for Post-Quantum IoT Designed and optimized a hardware accelerator for the Ascon -128 authenticated encryption algorithm targeting resource-constrained

Electrical Engineering undergraduate with strong hands-on experience in processor microarchitecture, FPGA-based system design, and hardware implementation of cryptographic algorithms. Proven capability in designing and verifying RISC-V processors (single- cycle and pipelined), integrating SoC components, and developing secure hardware accelerators for post-quantum IoT applications. Currently serving as an Undergraduate Research Assistant, working on high-performance, area-efficient implementations of Post Quantum Cryptographic Algorithm with a focus on throughput optimization and side-channel security. Demonstrates practical problem-solving ability, continuous learning, and a research-driven approach to digital system and processor-level security design. To continue my passion and contribute to open source, I have a Github repository, below is my attached Github Repositry. https://github.com/abdulhannanadil