Faareha Sajjad

PROFESSIONAL PROFILE I am an Electrical Engineering undergraduate specializing in analog IC design, with hands-on experience in transistor-level circuit design and physical layout using Cadence Virtuoso. I have worked on designing, simulating, and validating CMOS analog blocks, including instrumentation amplifiers, and bring strong analytical skills supported by experience in MATLAB, Python, and AI prompt engineering. EDUCATION Bachelor's of Electrical Engineering SEECS , Islamabad , 2.48 (2026) INTERNSHIP EXPERIENCE MiNE Lab, SEECS 23-Jun-2025 - 22-Aug-2025 - Developed transistor-level schematics in Cadence Virtuoso, performing simulations to validate circuit performance and specifications - Executed physical layouts for analog blocks, focusing on floorplanning, device placement, and routing techniques FINAL YEAR PROJECT Design of CMOS Instrumentation Amplifier for Spectroscopic Skin Bioimpedance Characterization Skin impedance can offer clinically relevant information such as skin cancer and skin hydration. Four wire measurements are proposed to characterize the impedance of skin layers beneath the highly insulation, superficial stratum corneum. Skin bioimpedance system requires a voltage source to inject current into skin through the pair of force electrodes. In addition, an instrumentation amplifier is required to measure the resulting voltage across the pair of sense electrodes. A transimpedance amplifier is also required to measure the injected current. Since bioimpedance is frequency dependent, skin impedance is generally characterized over a frequency spectrum. This project aims to design and implement a high-performance analog IC for IA using Vituoso Cadence, includig both schematic design and layout for integration into skin bioimpedance measurement systems. Virtuoso Cadence is a major tool in semiconductor design, enabling efficient development of high-performance analog ICs. TECHNICAL EXPERTISE Analog IC Design Strong foundation in analog IC design with solid theoretical understanding of CMOS device physics, amplifiers, current mirrors, and frequency response. Experienced in translating theory into practice by designing, simulating, and validating analog circuits using Cadence tools, including schematic capture, sim ...

I am an Electrical Engineering undergraduate specializing in analog IC design, with hands-on experience in transistor-level circuit design and physical layout using Cadence Virtuoso. I have worked on designing, simulating, and validating CMOS analog blocks, including instrumentation amplifiers, and bring strong analytical skills supported by experience in MATLAB, Python, and AI prompt engineering.