Fatima Tariq

PROFESSIONAL PROFILE Objective: Motivated Electrical Engineering undergraduate with strong expertise in computer architecture, VLSI design, embedded systems, and AI hardware acceleration, seeking industry roles to develop high-performance, energy-efficient in-memory computing and machine learning hardware solutions. Professional Summary: Detail-oriented Electrical Engineering student with hands-on experience in in-memory computing (IMC) architectures and AI accelerators, including RTL design and preparation for chip tape-out. Strong understanding of transformers, memory hierarchies (SRAM/DRAM), and hardware–software co-design for machine learning workloads. Proven ability to analyze research papers, translate theory into microarchitectural insights, and communicate complex technical concepts clearly in presentations and reports. Actively engaged in academic research projects and innovation-driven competitions, with a strong interest in energy-efficient and scalable computing systems. EDUCATION EE SEECS , Faisalabad , 3.55 (2022) INTERNSHIP EXPERIENCE SoC Lab 18-Jun-2025 - 22-Aug-2026 During my internship at the SOC Lab under the supervision of Professor Iman, I was assigned tasks focused on strengthening my foundation in Computer Architecture, gaining hands-on experience with Cadence EDA tools through lab sessions, and developing an understanding of the RTL-to-GDSII design flow. This journey enhanced both my theoretical knowledge and practical skills in VLSI design, while also giving me exposure to industry-standard tools and methodologies. FINAL YEAR PROJECT Impact-SoC The rapid growth of AI and data-intensive applications exposes the memory wall of von Neumann architectures, where excessive data movement between compute and memory degrades performance and energy efficiency. In-Memory Computing (IMC) addresses this limitation by performing arithmetic directly within memory arrays. Building upon a prior SRAM-based In-Memory Computing Unit (IMCU) integrated with a RISC-V SoC, the IMPACT SoC advances this work through architectural optimization, thorough RTL verification, and chip-ready physical design. The proposed system integrates an enhanced in-memory vector processing engine with a RISC-V core, an optimized DMA subsystem, and improved accumulation structures to achieve higher throughput, lower latency, and efficient parallel computation. The final outcome is a synthesizable, verified, and physically realizable in-memory accelerator, demonstrating the potential of IMC for energy-efficient AI and edge computing applications. TECHNICAL EXPERTISE Computer Architecture RISC-V pipeline design, processor datapath & control, memory hierarchy fundamentals

Objective: Motivated Electrical Engineering undergraduate with strong expertise in computer architecture, VLSI design, embedded systems, and AI hardware acceleration, seeking industry roles to develop high-performance, energy-efficient in-memory computing and machine learning hardware solutions. Professional Summary: Detail-oriented Electrical Engineering student with hands-on experience in in-memory computing (IMC) architectures and AI accelerators, including RTL design and preparation for chip tape-out. Strong understanding of transformers, memory hierarchies (SRAM/DRAM), and hardware–software co-design for machine learning workloads. Proven ability to analyze research papers, translate theory into microarchitectural insights, and communicate complex technical concepts clearly in presentations and reports. Actively engaged in academic research projects and innovation-driven competitions, with a strong interest in energy-efficient and scalable computing systems.