Umer Farooq

PROFESSIONAL PROFILE Final-year Electrical Engineering student at the National University of Sciences and Technology (NUST), SEECS, with a strong academic foundation and a focused interest in chip design and computer architecture. Currently completing a Final Year Project in collaboration with the Nust Chip Design Centre (NCDC), gaining hands-on exposure to processor design, hardware architecture, and digital system development. Possess six months of industry-relevant experience at NCDC, including three months as a trainee followed by three months as a project intern, contributing to real-world research and development tasks in digital and VLSI systems. Demonstrated ability to work in structured engineering environments, adapt quickly to complex technical challenges, and apply theoretical knowledge to practical implementations. Highly motivated to pursue a career in semiconductor design, processor architecture, and advanced digital systems, with a strong commitment to continuous learning and innovation in cutting-edge technologies. EDUCATION Electrical Engineering SEECS Nust , Islamabad , 3.23 (2026) INTERNSHIP EXPERIENCE Nust Chip Design Centre 18-Feb-2025 - 29-Aug-2025 Completed a six-month internship at NCDC, with the first three months as a trainee and the following three months as a project intern, during which we worked on a RISC-V RV32I processor FINAL YEAR PROJECT Design of a RISC-V based Symmetric Multi-processor Architecture The project involves design, implementation and verification of a RISC-V based Symmetric multiprocessor (SMP) architecture. As processor’s frequency can’t be scaled beyond a certain limit without compromising on power consumption, multiprocessors is a promising solution for improving performance without compromising power consumption. Objectives: • Design a RISC-V based SMP architecture and simulating it in gem5 simulator for performance analysis • Implement the design in RTL and perform design verification in UVM • Physical design of the SMP architecture (RTL to GDS-II) TECHNICAL EXPERTISE RISC-V Processor Architecture & VLSI Design Hands-on experience in the design, implementation, and verification of a RISC-V–based Symmetric Multiprocessor (SMP) architecture. Skilled in architectural modeling and performance evaluation using the gem5 simulator, with a focus on scalability and power-performance trade-offs. Proficient in RTL design and f ...

Final-year Electrical Engineering student at the National University of Sciences and Technology (NUST), SEECS, with a strong academic foundation and a focused interest in chip design and computer architecture. Currently completing a Final Year Project in collaboration with the Nust Chip Design Centre (NCDC), gaining hands-on exposure to processor design, hardware architecture, and digital system development. Possess six months of industry-relevant experience at NCDC, including three months as a trainee followed by three months as a project intern, contributing to real-world research and development tasks in digital and VLSI systems. Demonstrated ability to work in structured engineering environments, adapt quickly to complex technical challenges, and apply theoretical knowledge to practical implementations. Highly motivated to pursue a career in semiconductor design, processor architecture, and advanced digital systems, with a strong commitment to continuous learning and innovation in cutting-edge technologies.