Hasnat Ahmed Gill

PROFESSIONAL PROFILE Electrical Engineering undergraduate with expertise in FPGA-based design and Verilog RTL. Research includes secure hardware design for cryptographic and post-quantum systems, RISC-V processors, computer architecture techniques for performance optimization and floating-point architecture. Skilled in algorithm-to-hardware mapping, MATLAB/Simulink modeling, and performance optimization for cryptographic and DSP applications. EDUCATION No education information provided. INTERNSHIP EXPERIENCE ESDAC Research Laboratory NUST 17-Jun-2024 - 30-Aug-2024 Developed and deployed embedded software on Intel DE1-SoC board running an embedded Linux environment. I Implemented hardware–software co-design workflows for ARM–FPGA integration and then optimized Linux device drivers and peripheral interfacing for high-performance embedded applications. After that conducted cross-compilation and debugging using GCC toolchain and on-board JTAG/UART interfaces and contributed to research in real-time embedded systems and FPGA-based prototyping for industrial use cases. System on Chip Lab 31-Aug-2024 - 30-Sep-2024 I have developed and implemented processor designs in Verilog to strengthen my understanding of computer architecture. My work includes designing and simulating digital systems with optimized multiplier architectures, such as Dadda and Wallace tree multipliers. I have also implemented digital encoding and signal processing modules on FPGA platforms for real-time hardware validation, gaining hands-on experience with FPGA design workflows, RTL development, simulation, synthesis, and digital logic optimization. System on Chip Lab 23-Jun-2025 - 28-Jan-2026 I conducted research on secure hardware design for lightweight cryptography, focusing on the ASCON algorithm. I designed a hardware accelerator architecture for ASCON using Verilog RTL and implemented it on FPGA platforms. My work included developing key and nonce generation modules using LFSR-based randomness, as well as implementing the initialization and permutation rounds of the ASCON cipher on the DE1-SoC board. I also analyzed performance trade-offs in terms of area, throughput, and latency to evaluate and optimize the hardware cryptographic design. FINAL YEAR PROJECT No project information available. TECHNICAL EXPERTISE

Electrical Engineering undergraduate with expertise in FPGA-based design and Verilog RTL. Research includes secure hardware design for cryptographic and post-quantum systems, RISC-V processors, computer architecture techniques for performance optimization and floating-point architecture. Skilled in algorithm-to-hardware mapping, MATLAB/Simulink modeling, and performance optimization for cryptographic and DSP applications.